1. Field of the Invention
The invention relates in general to an elastomer interposer employed between the package and PCB and the method of manufacturing the same, and more particularly to an elastomer interposer functioning as a strain reliever for the solder balls between the package and the PCB, thus greatly enhance the reliability of the package against the thermal cycle failure.
2. Description of the Related Art
The integrated circuit (IC) devices can be packaged by a variety of the exterior packaging materials, so that IC can be mounted on the printed circuit board (PCB) and the functions of IC and heat dissipation are also achieved. In assembling IC onto the PCB, the conventional method of pin through hole (PTH) is mostly replaced by the surface mount technology (SMT), in order to increase the assembly efficiency and density of IC package.
The PTH method means that the insertion of component leads into via holes on the PCB for connecting and soldering the IC to the PCB. Dual inline package (DIP) is one sort of PTH-style assembly. The SMT method means that IC is soldered onto the PCB at high temperature by the solder balls or solder pastes on the PCB pads, instead of insertion of component leads. Due to its great potentials in reducing the PCB size, decreasing the production cost and raising the yield of production, the SMT-style assembly has become the mainstream in the IC packaging technology. Also, the packages suitable for SMT-style assembly could be the Grid Array (GA) packages, such as Pin Grid Array (PGA), Ball Grid Array (BGA) and Land Grid Array (LGA) packages.
FIG. 1A depicts the cross-sectional drawing of a conventional LGA packages. The package 102 includes the IC 104, substrate 106, molding compound 108, and gold wires 110a and 110b. The bottom surface 104b of the IC 104 adheres to the top surface 106a of the substrate 106 by the silver epoxy 112. The top surface 104a of the IC 104 which has the IC input/output (I/O) pads is electrically connected to the substrate 104 by the gold wires 110a and 110b. In FIG. 1A, the gold wires 110a and 110b connect the IC 104 and the openings (in that is electroplated with Ni/Au and named bonding finger)of the solder resistant layer 118a of the substrate 106. The substrate 106 further includes the vias 114, Ni/Au plated contact land pads 116, and the solder resistant layers 118a and 118b. The solder resistant layers 118a and 118b are on the top surface 106a and the bottom surface 106b of the substrate 106, respectively. The Ni/Au plated contact land pads 116 are in the openings of the solder resistant layer 118b for improving the electrical connection. Also, the metal traces are distributed underneath the solder resistant layers 118a and 118b for electrically connecting in the vias 114, the Ni/Au plated contact land pads 116 and the gold wires 110a and 110b. Also, the vias 114 created between the solder resistant layers 118a and 118b and the traces, are to electrically connect the Ni/Au plated contact land pads 116 and the gold wires 110a and 110b. Additionally, the molding compound 108, which is formed over the substrate 106 and made from high humidity-resistance material, encapsulates the IC 104 and the gold wires 110a and 110b for the purpose of protecting the wire bonded IC. The molding compound 108 not only prevents the wire bonded IC from corrosion (mainly caused by air and humidity), but also reduce the chance of physical destruction of the IC 104.
The Ni/Au plated contact land pads 116 form an array in the openings of the solder resistant layer 118b, as the name LGA (Land Grid Array) implies. If the solder balls are further attached onto the Ni/Au plated contact land pads 116, the package 102 becomes a BGA-style package 122, as shown in FIG. 1B. FIG. 1B is a schematic drawing of BGA package, and it clearly depicts the positions of the solder balls 120. Furthermore, the package 122 is named as a plastic ball grid array (PBGA) package if the substrate 106 and the molding compound 108 are made by organic materials. Similarly, the package 122 is named as a ceramic ball grid array (CBGA) package if the substrate 204 and the top lid 206 are made by ceramics.
FIG. 2 depicts a cross-sectional drawing of a CBGA package and a PCB. The CBGA package 202 includes a CBGA substrate 204 and a ceramic lid 206. The ceramic lid 206 glued over the top surface 204 of the CBGA substrate 204 functions as a hermetic seal. The solder balls 208 attached to the bottom surface 204b of the CBGA substrate 204 are joined to the solder ball pads 212 on the PCB 210 (along the direction of the arrow 220) at a high temperature. The coefficient of thermal expansion (CTE) of the CBGA substrate 204 is approximately 8 ppm/° C., while the CTE of the PCB 210 is approximately 18 ppm/° C. Therefore, the CBGA substrate 204 can not be reliably mounted on the epoxy-based PCB 210 due to the solder ball crack (stress fatigue) problem from future thermal cycles, of which is originated from the CTE mismatch between the PCB 210 and the CBGA package 202. According to the CTE mismatch between the PCB 210 and the CBGA package 202, during high-temperature bonding, the thermal expansion of the PCB 210 is greater than that of the ceramic substrate so as that there exerted two thermal stress on the solder balls 208 after cooling down. The solder balls 208 would crack and could not make the package 202 firmly mounted on the PCB 210.
FIG. 3 depicts a cross-sectional drawing of a PBGA package and a low-CTE PCB. In FIG. 3, the PBGA package 302 includes a PBGA substrate 304 and a molding compound 306. The molding compound 306 is formed over the top surface 304 of the PBGA substrate 304. The solder balls 308 attached to the bottom surface 304b of the PBGA substrate 304 are joined to the solder ball pads 312 on the PCB 310 (along the direction of the arrow 320) at a high temperature. The CTE of the PBGA substrate 304 is approximately 18 ppm/° C., larger than that of the low-CTE PCB 310, approximately 5˜10 ppm/° C. Therefore, the PBGA substrate 304 can not be reliably mounted on the epoxy-based PCB 310 due to the solder ball crack (stress fatigue) problem from future thermal cycles, of which is originated from the CTE mismatch between the PCB 310 and the PBGA package 302.
An elastomeric connector to connect integrated circuit chips in a microcircuit package for permanent interconnection or testing purposes is disclosed in U.S. Pat. No. 4,932,883, “Elastomeric connectors for electronic packaging and testing”, Hsia, et al. FIG. 4 is a cross-sectional drawing of an assembled IC, elastomeric connector and test substrate. The elastomeric connector 402 includes the elastomeric base 406, the through-hole conductors 408 and the surface conductor tabs 410. The elastomeric base 406 is placed over the top surface 404a of the test substrate 404. The through-hole conductors 408 are embedded in the elastomeric base 406 and vertically attached to the top surface 404a of the test substrate 404. The through-hole conductors 408 make direct contact with the metal lines of the test substrate 404. The surface conductor tabs 410 exist on the top surface of the elastomeric base 406 and are connected to each of the through-hole conductors 408. The plates 416a and 416b clip the IC 412, the elastomeric connector 402 and the test substrate 404 by a clamping means such as the screws 418a and 418b. The through-hole conductors 408 are not deformed, while the surface conductor tabs 410 slightly bend due to the downward pressure. The elastomeric base 406 is also deformed by the clamping force of the plates 416a and 416b, so that the I/O pads (I/O solder balls) 414 can make good electrical contact with the surface conductor tabs 410.
Since the I/O pads (I/O solder balls) 414 contact with the surface conductor tabs 410 instead of soldering, thermal expansion and contraction of the IC 412, elastomeric connector 402 and test substrate 404 caused by temperature change has no effect on the electrical connection between the I/O pads 414 and the surface conductor tabs 410. This configuration will turn the CTE differences between the IC 412, elastomeric connector 402 and test substrate 404 into an insignificant factor, and the I/O solder balls 414 crack from thermal stress can be prevented.
Since only one through-hole conductors 408 for one surface conductor tabs 410, the numbers of disposed I/O solder balls 414 and through-hole conductors 408 are limited; consequently, the elastomeric connector 402 is only suitable and applicable to a package which has the I/O solder balls 414 as many as the through-hole conductors 408. Besides, only small area of the elastomeric connector 402 (the portion beneath the surface conductor tabs 410) bears the clamping force. The through-hole conductors 408 and the surface conductor tabs 410, made by metal and with little elasticity, could be damaged or even broken when the assembly suffers from an over large clamping force or collision. Moreover, the surface conductor tabs 410 are disposed over the top surface of elastomeric base 406 only. The bottom surface 404a has no surface conductor tabs 410 and the application of this elastomeric connector 402 is therefore limited. Also, no surface insulating layer is adopted in the elastomeric connector 402 to isolate adjacent surface conductor tabs 410, and this may easily introduce short circuit and poor humidity resistance reliability.